«The EFM-02 embedded FPGA module is based on the Xilinx Spartan-6LX® FPGA. This FPGA family delivers an optimal balance of low risk, low cost, and low power for cost-sensitive applications. With integrated power supplies, platform flash and reference designs, the EFM-02 provides everything to build custom cameras, image processing systems or any other high-performance FPGA-based systems.»
Real-world measured data rate of more than 300 MB/s can be achieved with the UDK3 API and SuperSpeed USB 3.0 connections.
A suitable AXI4 busmastering IP (GPIF2AXI4) is included in the UDK3. Just drop it in your EDK design and access your local AXI4 bus from a PC over USB 3.0. The Cesys UDK API calls provide read and write functions to addressable blocks of data remotely on your local AXI4 bus. It works as easy as memcopy does locally on your PC. Of course, the GPIF2AXI4 IP core can reside in parallel to other busmasters, like Xilinx Microblaze® processors.
For developers who do not plan to use the EDK design flow, there is a VHDL-based IP targeting the Wishbone bus. Both IPs come with example designs.
You can configure the FPGA using the Xilinx Platform Cable (JTAG), using your own UDK-based software, using the UDK3 board manager or from the on-board flash memory. All this options are always available - there is no need to choose by setting switches or jumpers.
With up to 191 user-IO, which can also be used as differential pairs, the EFM02 offers ample connectivity options.
The on-board 2 Gbit DDR2 SDRAM (eq. 256 MByte) provides plentiful memory capacity - ideal for applications like image processing or data acquisition.
Included in the UDK, there are tools to perform FPGA configuration, clear, write and read the on-board configuration flash, read and write the user-ID of the board and control the reset-pin.
The Cesys UDK is an API for FPGA configuration and interfacing the FPGA to the software running on your PC. The UDK handles everything between a API call from your software and a Wishbone or AXI4 bus transaction inside the FPGA. Read and write calls are serialized through the USB 3.0 bus, making the FPGA bus address space directly accessible by your software. Using the UDK results in an enormous saving in time and development resources. The UDK comes with no additional cost in binary form with the EFM-02 module. To use it with 3rd party hardware, we offer a pay-once source-code licensing model for the UDK source-code.
Use our extensively tested reference designs as a starting point for your projects. We use our own reference designs for many customer projects and can therefore offer you the very best support.
We have great interest in ensuring that your project is successful. That is why we will give great effort to assist you. We will answer questions that you ask in our support-forum as soon as possible because sometimes, it's the little things that stop you. In addition to our free forum-support, we offer fee-based support and development service customized to your needs.
The EFM-02 was built for prototyping systems and integration into OEM devices. Everywhere, a flexible FPGA solution with USB 3.0 interface is required, the EFM-02 is a perfect match.
|device||logic cells||CLB flip-flops||distributed RAM bits||block RAM bits||DSP48A1 slices1||CMTs2|
1 Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator
2 Each CMT contains two DCMs and one PLL
To develop your own FPGA solutions, Xilinx offers the ISE design suite.
The XC6SLX45 FPGA is supported by the free version, called WebPack Edition.
The XC6SLX100 and XC6SLX150 FPGAs are supported by all other ISE Design Suite editions.
Get answers, download* drivers, tools and reference designs from the Cesys support forum.
* To enter the protected download area of the forum, you have to register in the forum and ask the forum admin to flag you as a customer.
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