################################################################################ ## copyright notice: ################################################################################ ## copyright (c) 2010 by ## ## CESYS GmbH / GERMANY ## ## http://www.cesys.com ################################################################################ ## author: ################################################################################ ## Manfred Kraus ################################################################################ ## license: ################################################################################ ## THIS SOURCECODE IS NOT FREE! IT IS FOR USE TOGETHER WITH CESYS PRODUCTS ONLY! ## YOU ARE NOT ALLOWED TO MODIFY AND DISTRIBUTE OR USE IT WITH ANY OTHER ## HARDWARE, SOFTWARE OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN ## WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT HOLDER! ################################################################################ ## disclaimer of warranty: ################################################################################ ## THIS SOURCECODE IS DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL, BUT ## THERE IS NO WARRANTY OR SUPPORT FOR THIS SOURCECODE. THE COPYRIGHT HOLDER ## PROVIDES THIS SOURCECODE "AS IS" WITHOUT WARRANTY OF ANY KIND, ## EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. ## THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THIS SOURCECODE IS WITH ## YOU. SHOULD THIS SOURCECODE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL ## NECESSARY SERVICING, REPAIR OR CORRECTION. ## ## IN NO EVENT WILL THE COPYRIGHT HOLDER BE LIABLE TO YOU FOR DAMAGES, INCLUDING ## ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE ## USE OR INABILITY TO USE THIS SOURCECODE (INCLUDING BUT NOT LIMITED TO LOSS OF ## DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD ## PARTIES OR A FAILURE OF THIS SOURCECODE TO OPERATE WITH ANY OTHER ## SOFTWARE-PROGRAMS, HARDWARE-CIRCUITS OR ANY OTHER KIND OF ASIC OR ## PROGRAMMABLE LOGIC DESIGN), EVEN IF THE COPYRIGHT HOLDER HAS BEEN ADVISED OF ## THE POSSIBILITY OF SUCH DAMAGES. ################################################################################ ############################################################################ ## Clock constraints ############################################################################ #Will be automatically derived from 100 MHz clock driving the PLL NET "pin_clk100_i" TNM_NET = "pin_clk100_i"; TIMESPEC TS_pin_clk100_i = PERIOD "pin_clk100_i" 10 ns HIGH 50 %; NET "pin_gpifclk_i" TNM_NET = "pin_gpifclk_i"; TIMESPEC TS_pin_gpifclk_i = PERIOD "pin_gpifclk_i" 10 ns HIGH 50 %; # following specs are for PCLK = 100 MHz (10ns) TIMEGRP "FD" OFFSET = IN 2 ns VALID 2 ns BEFORE "pin_gpifclk_i"; #TIMEGRP "FD" OFFSET = OUT 8 ns VALID 10 ns AFTER "pin_gpifclk_i"; TIMEGRP "FD" OFFSET = OUT 8 ns AFTER "pin_gpifclk_i"; TIMEGRP "FLAGS" OFFSET = IN 2 ns VALID 2 ns BEFORE "pin_gpifclk_i" RISING; TIMEGRP "CTRL" OFFSET = OUT 8 ns AFTER "pin_gpifclk_i"; NET "pin_clk100_i" IOSTANDARD = LVCMOS33 | LOC = W12; NET "pin_gpifclk_i" IOSTANDARD = LVCMOS33 | LOC = Y12; NET "pin_gpifclk_o" DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = W11; NET "pin_sysreset_i" IOSTANDARD = LVCMOS33 | LOC = AB19 | PULLUP; NET "pin_fx3_flag_i[0]" LOC = AA8 | TNM = "FLAGS" | IOSTANDARD = LVCMOS33 | PULLUP; NET "pin_fx3_flag_i[1]" LOC = AA14 | TNM = "FLAGS" | IOSTANDARD = LVCMOS33 | PULLDOWN; NET "pin_fx3_flag_i[2]" LOC = Y17 | TNM = "FLAGS" | IOSTANDARD = LVCMOS33 | PULLUP; NET "pin_fx3_flag_i[3]" LOC = V11 | TNM = "FLAGS" | IOSTANDARD = LVCMOS33 | PULLUP; NET "pin_fx3_slrd_n_o" TNM = "CTRL" |DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB9 | PULLUP; NET "pin_fx3_slwr_n_o" TNM = "CTRL" |DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 |LOC = AB4 | PULLUP; NET "pin_fx3_sloe_n_o" TNM = "CTRL" |DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 |LOC = Y3 | PULLUP; NET "pin_fx3_slcs_n_o" TNM = "CTRL" |DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 |LOC = AB3 | PULLUP; NET "pin_fx3_pktend_n_o" TNM = "CTRL" |DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB8; NET "pin_fx3_fifoadr_o[0]" TNM = "CTRL" |DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = Y19; NET "pin_fx3_fifoadr_o[1]" TNM = "CTRL" |DRIVE = 24 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = Y9; # SSO (simultanous switching outputs) rules are only met when DRIVE = 12 or less. NET "pin_fx3_fd_io[0]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB21; NET "pin_fx3_fd_io[1]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = U14; NET "pin_fx3_fd_io[2]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = U13; NET "pin_fx3_fd_io[3]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AA6; NET "pin_fx3_fd_io[4]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB6; NET "pin_fx3_fd_io[5]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = W4; NET "pin_fx3_fd_io[6]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = Y4; NET "pin_fx3_fd_io[7]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = Y7; NET "pin_fx3_fd_io[8]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AA2; NET "pin_fx3_fd_io[9]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB2; NET "pin_fx3_fd_io[10]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = V15; NET "pin_fx3_fd_io[11]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AA18; NET "pin_fx3_fd_io[12]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB18; NET "pin_fx3_fd_io[13]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = Y13; NET "pin_fx3_fd_io[14]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AA12; NET "pin_fx3_fd_io[15]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB12; NET "pin_fx3_fd_io[16]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB15; NET "pin_fx3_fd_io[17]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = V9; NET "pin_fx3_fd_io[18]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB16; NET "pin_fx3_fd_io[19]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AA16; NET "pin_fx3_fd_io[20]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = T15; NET "pin_fx3_fd_io[21]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB17; NET "pin_fx3_fd_io[22]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = T16; NET "pin_fx3_fd_io[23]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB10; NET "pin_fx3_fd_io[24]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = V17; NET "pin_fx3_fd_io[25]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = AB14; NET "pin_fx3_fd_io[26]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = Y15; NET "pin_fx3_fd_io[27]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = Y18; NET "pin_fx3_fd_io[28]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = W17; NET "pin_fx3_fd_io[29]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = W18; NET "pin_fx3_fd_io[30]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = T17; NET "pin_fx3_fd_io[31]" TNM = "FD" | DRIVE = 12 | SLEW = FAST | IOSTANDARD = LVCMOS33 | LOC = T18; # User Led NET "pin_user_led_o" SLEW = SLOW | DRIVE = 12 | IOSTANDARD = LVCMOS18 | LOC = A2; # IO_L83P3 # Flash Memory NET "pin_cfg_flash_s_n_o" SLEW = FAST | DRIVE = 12 | IOSTANDARD = LVCMOS33 | LOC = T5; # IO_L65N2_CSO_B NET "pin_cfg_flash_c_o" SLEW = FAST | DRIVE = 12 | IOSTANDARD = LVCMOS33 | LOC = Y21; # IO_L1P2_CCLK NET "pin_cfg_flash_d_o" SLEW = FAST | DRIVE = 12 | IOSTANDARD = LVCMOS33 | LOC = AB20; # IO_L3N2_MOSI_CSI_B_MISO0 NET "pin_cfg_flash_q_i" SLEW = FAST | DRIVE = 12 | IOSTANDARD = LVCMOS33 | LOC = AA20; # IO_L3P2_D0_DIN_MISO_MISO1 # LOC gpio signals: pin_io_____ # ############################################################################################################## # io bank 0 # # valid IO pins for XC6SLX25, XC6SLX45, XC6SLX75, XC6SLX100, XC6SLX150 # ############################################################################################################## NET "pin_gpio*" TIG; # ignore Timing for GPIO signals NET "pin_gpio[*]" PULLDOWN; NET "pin_gpio[0]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A3; # pin_io_B0_L1P0_hswapen_A3_J1_86 -> IO_FPGA_BANK0_IO0 (has external pull-up) NET "pin_gpio[1]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A4; # pin_io_B0_L1N0_vref0_A4_J1_88 -> IO_FPGA_BANK0_IO1 NET "pin_gpio[2]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C5; # pin_io_B0_L2P0_C5_J1_60 -> IO_FPGA_BANK0_IO2 NET "pin_gpio[3]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A5; # pin_io_B0_L2N0_A5_J1_58 -> IO_FPGA_BANK0_IO3 NET "pin_gpio[4]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D6; # pin_io_B0_L3P0_D6_J1_42 -> IO_FPGA_BANK0_IO4 NET "pin_gpio[5]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C6; # pin_io_B0_L3N0_C6_J1_44 -> IO_FPGA_BANK0_IO5 NET "pin_gpio[6]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B6; # pin_io_B0_L4P0_B6_J1_76 -> IO_FPGA_BANK0_IO6 NET "pin_gpio[7]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A6; # pin_io_B0_L4N0_A6_J1_74 -> IO_FPGA_BANK0_IO7 NET "pin_gpio[8]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C7; # pin_io_B0_L5P0_C7_J1_30 -> IO_FPGA_BANK0_IO8 NET "pin_gpio[9]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A7; # pin_io_B0_L5N0_A7_J1_32 -> IO_FPGA_BANK0_IO9 NET "pin_gpio[10]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B8; # pin_io_B0_L6P0_B8_J1_29 -> IO_FPGA_BANK0_IO10 NET "pin_gpio[11]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A8; # pin_io_B0_L6N0_A8_J1_31 -> IO_FPGA_BANK0_IO11 NET "pin_gpio[12]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D9; # pin_io_B0_L7P0_D9_J1_52 -> IO_FPGA_BANK0_IO12 NET "pin_gpio[13]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C8; # pin_io_B0_L7N0_C8_J1_50 -> IO_FPGA_BANK0_IO13 NET "pin_gpio[14]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C9; # pin_io_B0_L8P0_C9_J1_34 -> IO_FPGA_BANK0_IO14 NET "pin_gpio[15]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A9; # pin_io_B0_L8N0_vref0_A9_J1_36 -> IO_FPGA_BANK0_IO15 NET "pin_gpio[16]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D7; # pin_io_B0_L32P0_D7_J1_46 -> IO_FPGA_BANK0_IO16 NET "pin_gpio[17]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D8; # pin_io_B0_L32N0_D8_J1_48 -> IO_FPGA_BANK0_IO17 NET "pin_gpio[18]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D10; # pin_io_B0_L33P0_D10_J1_25 -> IO_FPGA_BANK0_IO18 NET "pin_gpio[19]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C10; # pin_io_B0_L33N0_C10_J1_27 -> IO_FPGA_BANK0_IO19 NET "pin_gpio[20]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B10; # pin_io_B0_L34P0_GCLK19_B10_J1_23 -> IO_FPGA_BANK0_IO20 NET "pin_gpio[21]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A10; # pin_io_B0_L34N0_GCLK18_A10_J1_21 -> IO_FPGA_BANK0_IO21 NET "pin_gpio[22]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C11; # pin_io_B0_L35P0_GCLK17_C11_J1_65 -> IO_FPGA_BANK0_IO22 NET "pin_gpio[23]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A11; # pin_io_B0_L35N0_GCLK16_A11_J1_67 -> IO_FPGA_BANK0_IO23 NET "pin_gpio[24]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D11; # pin_io_B0_L36P0_GCLK15_D11_J1_37 -> IO_FPGA_BANK0_IO24 NET "pin_gpio[25]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C12; # pin_io_B0_L36N0_GCLK14_C12_J1_39 -> IO_FPGA_BANK0_IO25 NET "pin_gpio[26]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B12; # pin_io_B0_L37P0_GCLK13_B12_J1_94 -> IO_FPGA_BANK0_IO26 NET "pin_gpio[27]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A12; # pin_io_B0_L37N0_GCLK12_A12_J1_96 -> IO_FPGA_BANK0_IO27 NET "pin_gpio[28]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C13; # pin_io_B0_L38P0_C13_J1_43 -> IO_FPGA_BANK0_IO28 NET "pin_gpio[29]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A13; # pin_io_B0_L38N0_vref0_A13_J1_41 -> IO_FPGA_BANK0_IO29 NET "pin_gpio[30]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D14; # pin_io_B0_L49P0_D14_J1_57 -> IO_FPGA_BANK0_IO30 NET "pin_gpio[31]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C14; # pin_io_B0_L49N0_C14_J1_59 -> IO_FPGA_BANK0_IO31 NET "pin_gpio[32]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B14; # pin_io_B0_L50P0_B14_J1_47 -> IO_FPGA_BANK0_IO32 NET "pin_gpio[33]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A14; # pin_io_B0_L50N0_A14_J1_45 -> IO_FPGA_BANK0_IO33 NET "pin_gpio[34]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C15; # pin_io_B0_L51P0_C15_J1_63 -> IO_FPGA_BANK0_IO34 NET "pin_gpio[35]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A15; # pin_io_B0_L51N0_A15_J1_61 -> IO_FPGA_BANK0_IO35 NET "pin_gpio[36]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D15; # pin_io_B0_L62P0_D15_J1_79 -> IO_FPGA_BANK0_IO36 NET "pin_gpio[37]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C16; # pin_io_B0_L62N0_vref0_C16_J1_77 -> IO_FPGA_BANK0_IO37 NET "pin_gpio[38]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B16; # pin_io_B0_L63P0_SCP7_B16_J1_75 -> IO_FPGA_BANK0_IO38 NET "pin_gpio[39]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A16; # pin_io_B0_L63N0_SCP6_A16_J1_73 -> IO_FPGA_BANK0_IO39 NET "pin_gpio[40]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C17; # pin_io_B0_L64P0_SCP5_C17_J1_91 -> IO_FPGA_BANK0_IO40 NET "pin_gpio[41]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A17; # pin_io_B0_L64N0_SCP4_A17_J1_89 -> IO_FPGA_BANK0_IO41 NET "pin_gpio[42]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B18; # pin_io_B0_L65P0_SCP3_B18_J1_103 -> IO_FPGA_BANK0_IO42 NET "pin_gpio[43]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A18; # pin_io_B0_L65N0_SCP2_A18_J1_101 -> IO_FPGA_BANK0_IO43 NET "pin_gpio[44]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = E16; # pin_io_B0_L66P0_SCP1_E16_J1_81 -> IO_FPGA_BANK0_IO44 NET "pin_gpio[45]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D17; # pin_io_B0_L66N0_SCP0_D17_J1_83 -> IO_FPGA_BANK0_IO45 # ############################################################################################################## # io bank 1 # valid IO pins for XC6SLX25, XC6SLX45, XC6SLX75, XC6SLX100, XC6SLX150 # ############################################################################################################## NET "pin_gpio[46]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C19; # pin_io_B1_L1P1_A25_C19_J1_110 -> IO_FPGA_BANK1_IO0 NET "pin_gpio[47]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B20; # pin_io_B1_L1N1_A24_vref1_B20_J1_112 -> IO_FPGA_BANK1_IO1 NET "pin_gpio[48]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B21; # pin_io_B1_L19P1_B21_J1_105 -> IO_FPGA_BANK1_IO2 NET "pin_gpio[49]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = B22; # pin_io_B1_L19N1_B22_J1_107 -> IO_FPGA_BANK1_IO3 NET "pin_gpio[50]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A20; # pin_io_B1_L20P1_A20_J1_85 -> IO_FPGA_BANK1_IO4 NET "pin_gpio[51]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = A21; # pin_io_B1_L20N1_A21_J1_87 -> IO_FPGA_BANK1_IO5 NET "pin_gpio[52]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D19; # pin_io_B1_L29P1_A23_M1A13_D19_J2_117 -> IO_FPGA_BANK1_IO6 NET "pin_gpio[53]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D20; # pin_io_B1_L29N1_A22_M1A14_D20_J2_119 -> IO_FPGA_BANK1_IO7 NET "pin_gpio[54]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F18; # pin_io_B1_L30P1_A21_M1RESET_F18_J1_102 -> IO_FPGA_BANK1_IO8 NET "pin_gpio[55]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F19; # pin_io_B1_L30N1_A20_M1A11_F19_J1_104 -> IO_FPGA_BANK1_IO9 NET "pin_gpio[56]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D21; # pin_io_B1_L31P1_A19_M1CKE_D21_J2_114 -> IO_FPGA_BANK1_IO10 NET "pin_gpio[57]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D22; # pin_io_B1_L31N1_A18_M1A12_D22_J2_116 -> IO_FPGA_BANK1_IO11 NET "pin_gpio[58]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C20; # pin_io_B1_L32P1_A17_M1A8_C20_J1_118 -> IO_FPGA_BANK1_IO12 NET "pin_gpio[59]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = C22; # pin_io_B1_L32N1_A16_M1A9_C22_J1_120 -> IO_FPGA_BANK1_IO13 NET "pin_gpio[60]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G19; # pin_io_B1_L33P1_A15_M1A10_G19_J1_106 -> IO_FPGA_BANK1_IO14 NET "pin_gpio[61]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F20; # pin_io_B1_L33N1_A14_M1A4_F20_J1_108 -> IO_FPGA_BANK1_IO15 NET "pin_gpio[62]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H19; # pin_io_B1_L34P1_A13_M1WE_H19_J2_56 -> IO_FPGA_BANK1_IO16 NET "pin_gpio[63]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H18; # pin_io_B1_L34N1_A12_M1BA2_H18_J2_54 -> IO_FPGA_BANK1_IO17 NET "pin_gpio[64]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = E20; # pin_io_B1_L35P1_A11_M1A7_E20_J2_115 -> IO_FPGA_BANK1_IO18 NET "pin_gpio[65]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = E22; # pin_io_B1_L35N1_A10_M1A2_E22_J2_113 -> IO_FPGA_BANK1_IO19 NET "pin_gpio[66]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = J17; # pin_io_B1_L36P1_A9_M1BA0_J17_J2_60 -> IO_FPGA_BANK1_IO20 NET "pin_gpio[67]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = K17; # pin_io_B1_L36N1_A8_M1BA1_K17_J2_58 -> IO_FPGA_BANK1_IO21 NET "pin_gpio[68]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F21; # pin_io_B1_L37P1_A7_M1A0_F21_J2_110 -> IO_FPGA_BANK1_IO22 NET "pin_gpio[69]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F22; # pin_io_B1_L37N1_A6_M1A1_F22_J2_112 -> IO_FPGA_BANK1_IO23 NET "pin_gpio[70]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H20; # pin_io_B1_L38P1_A5_M1CLK_H20_J2_107 -> IO_FPGA_BANK1_IO24 NET "pin_gpio[71]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = J19; # pin_io_B1_L38N1_A4_M1CLKN_J19_J2_105 -> IO_FPGA_BANK1_IO25 NET "pin_gpio[72]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G20; # pin_io_B1_L39P1_M1A3_G20_J2_111 -> IO_FPGA_BANK1_IO26 NET "pin_gpio[73]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G22; # pin_io_B1_L39N1_M1ODT_G22_J2_109 -> IO_FPGA_BANK1_IO27 NET "pin_gpio[74]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = K20; # pin_io_B1_L40P1_GCLK11_M1A5_K20_J2_97 -> IO_FPGA_BANK1_IO28 NET "pin_gpio[75]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = K19; # pin_io_B1_L40N1_GCLK10_M1A6_K19_J2_99 -> IO_FPGA_BANK1_IO29 NET "pin_gpio[76]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H21; # pin_io_B1_L41P1_GCLK9_IRDY1_M1RASN_H21_J2_106 -> IO_FPGA_BANK1_IO30 NET "pin_gpio[77]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H22; # pin_io_B1_L41N1_GCLK8_M1CASN_H22_J2_108 -> IO_FPGA_BANK1_IO31 NET "pin_gpio[78]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = M20; # pin_io_B1_L42P1_GCLK7_M1UDM_M20_J2_79 -> IO_FPGA_BANK1_IO32 NET "pin_gpio[79]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = L19; # pin_io_B1_L42N1_GCLK6_TRDY1_M1LDM_L19_J2_77 -> IO_FPGA_BANK1_IO33 NET "pin_gpio[80]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = J20; # pin_io_B1_L43P1_GCLK5_M1DQ4_J20_J2_101 -> IO_FPGA_BANK1_IO34 NET "pin_gpio[81]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = J22; # pin_io_B1_L43N1_GCLK4_M1DQ5_J22_J2_103 -> IO_FPGA_BANK1_IO35 NET "pin_gpio[82]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = K21; # pin_io_B1_L44P1_A3_M1DQ6_K21_J2_102 -> IO_FPGA_BANK1_IO36 NET "pin_gpio[83]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = K22; # pin_io_B1_L44N1_A2_M1DQ7_K22_J2_104 -> IO_FPGA_BANK1_IO37 NET "pin_gpio[84]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = L20; # pin_io_B1_L45P1_A1_M1LDQS_L20_J2_100 -> IO_FPGA_BANK1_IO38 NET "pin_gpio[85]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = L22; # pin_io_B1_L45N1_A0_M1LDQSN_L22_J2_98 -> IO_FPGA_BANK1_IO39 NET "pin_gpio[86]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = M21; # pin_io_B1_L46P1_FCS_B_M1DQ2_M21_J2_94 -> IO_FPGA_BANK1_IO40 NET "pin_gpio[87]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = M22; # pin_io_B1_L46N1_FOE_B_M1DQ3_M22_J2_96 -> IO_FPGA_BANK1_IO41 NET "pin_gpio[88]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = N20; # pin_io_B1_L47P1_FWE_B_M1DQ0_N20_J2_93 -> IO_FPGA_BANK1_IO42 NET "pin_gpio[89]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = N22; # pin_io_B1_IO_L47N1_LDC_M1DQ1_N22_J2_95 -> IO_FPGA_BANK1_IO43 NET "pin_gpio[90]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = P21; # pin_io_B1_L48P1_HDC_M1DQ8_P21_J2_90 -> IO_FPGA_BANK1_IO44 NET "pin_gpio[91]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = P22; # pin_io_B1_L48N1_M1DQ9_P22_J2_92 -> IO_FPGA_BANK1_IO45 NET "pin_gpio[92]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R20; # pin_io_B1_L49P1_M1DQ10_R20_J2_89 -> IO_FPGA_BANK1_IO46 NET "pin_gpio[93]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R22; # pin_io_B1_L49N1_M1DQ11_R22_J2_91 -> IO_FPGA_BANK1_IO47 NET "pin_gpio[94]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T21; # pin_io_B1_L50P1_M1UDQS_T21_J2_86 -> IO_FPGA_BANK1_IO48 NET "pin_gpio[95]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T22; # pin_io_B1_L50N1_M1UDQSN_T22_J2_88 -> IO_FPGA_BANK1_IO49 NET "pin_gpio[96]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U20; # pin_io_B1_L51P1_M1DQ12_U20_J2_48 -> IO_FPGA_BANK1_IO50 NET "pin_gpio[97]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U22; # pin_io_B1IO_L51N1_M1DQ13_U22_J2_46 -> IO_FPGA_BANK1_IO51 NET "pin_gpio[98]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V21; # pin_io_B1_L52P1_M1DQ14_V21_J2_82 -> IO_FPGA_BANK1_IO52 NET "pin_gpio[99]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V22; # pin_io_B1_L52N1_M1DQ15_V22_J2_84 -> IO_FPGA_BANK1_IO53 NET "pin_gpio[100]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = M19; # pin_io_B1_L53P1_M19_J2_67 -> IO_FPGA_BANK1_IO54 NET "pin_gpio[101]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = N19; # pin_io_B1_L53N1_VREF1_N19_J2_65 -> IO_FPGA_BANK1_IO55 NET "pin_gpio[102]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = P19; # pin_io_B1_L59P1_P19_J2_42 -> IO_FPGA_BANK1_IO56 NET "pin_gpio[103]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = P20; # pin_io_B1_L59N1_P20_J2_44 -> IO_FPGA_BANK1_IO57 NET "pin_gpio[104]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W20; # pin_io_B1_L60P1_W20_J2_69 -> IO_FPGA_BANK1_IO58 NET "pin_gpio[105]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W22; # pin_io_B1_L60N1_W22_J2_71 -> IO_FPGA_BANK1_IO59 NET "pin_gpio[106]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = L17; # pin_io_B1_L61P1_L17_J2_76 -> IO_FPGA_BANK1_IO60 NET "pin_gpio[107]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = K18; # pin_io_B1_L61N1_K18_J2_74 -> IO_FPGA_BANK1_IO61 NET "pin_gpio[108]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T19; # pin_io_B1_74P1_AWAKE_T19_J2_51 -> IO_FPGA_BANK1_IO62 NET "pin_gpio[109]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T20; # pin_io_B1_L74N1_DOUT_BUSY_T20_J2_49 -> IO_FPGA_BANK1_IO63 # ############################################################################################################## # io bank 1 # valid IO pins for XC6SLX45, XC6SLX75, XC6SLX100, XC6SLX150 # ############################################################################################################## NET "pin_gpio[110]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G16; # pin_io_B1_L9P1_G16_J1_93 -> IO_FPGA_BANK1_OPT_IO0 NET "pin_gpio[111]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G17; # pin_io_B1_L9N1_G17_J1_95 -> IO_FPGA_BANK1_OPT_IO1 NET "pin_gpio[112]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F16; # pin_io_B1_L10P1_F16_J1_97 -> IO_FPGA_BANK1_OPT_IO2 NET "pin_gpio[113]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F17; # pin_io_B1_L10N1_F17_J1_99 -> IO_FPGA_BANK1_OPT_IO3 NET "pin_gpio[114]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = K16; # pin_io_B1_L21P1_K16_J2_78 -> IO_FPGA_BANK1_OPT_IO4 NET "pin_gpio[115]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = J16; # pin_io_B1_L21N1_J16_J2_80 -> IO_FPGA_BANK1_OPT_IO5 NET "pin_gpio[116]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H16; # pin_io_B1_L28P1_H16_J1_98 -> IO_FPGA_BANK1_OPT_IO6 NET "pin_gpio[117]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H17; # pin_io_B1_L28N1_VREF1_H17_J1_100 -> IO_FPGA_BANK1_OPT_IO7 NET "pin_gpio[118]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = M16; # pin_io_B1_L58P1_M16_J2_50 -> IO_FPGA_BANK1_OPT_IO8 NET "pin_gpio[119]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = L15; # pin_io_B1_L58N1_L15_J2_52 -> IO_FPGA_BANK1_OPT_IO9 NET "pin_gpio[120]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U19; # pin_io_B1_L70P1_U19_J2_75 -> IO_FPGA_BANK1_OPT_IO10 NET "pin_gpio[121]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V20; # pin_io_B1_L70N1_V20_J2_73 -> IO_FPGA_BANK1_OPT_IO11 NET "pin_gpio[122]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = M17; # pin_io_B1_L71P1_M17_J2_70 -> IO_FPGA_BANK1_OPT_IO12 NET "pin_gpio[123]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = M18; # pin_io_B1_L71N1_M18_J2_72 -> IO_FPGA_BANK1_OPT_IO13 NET "pin_gpio[124]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = P17; # pin_io_B1_L72P1_P17_J2_66 -> IO_FPGA_BANK1_OPT_IO14 NET "pin_gpio[125]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = N16; # pin_io_B1_L72N1_N16_J2_68 -> IO_FPGA_BANK1_OPT_IO15 NET "pin_gpio[126]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = P18; # pin_io_B1_L73P1_P18_J2_55 -> IO_FPGA_BANK1_OPT_IO16 NET "pin_gpio[127]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R19; # pin_io_B1_L73N1_R19_J2_53 -> IO_FPGA_BANK1_OPT_IO17 # ############################################################################################################## # io bank 2 # valid IO pins for XC6SLX25, XC6SLX45, XC6SLX75, XC6SLX100, XC6SLX150 # ############################################################################################################## NET "pin_gpio[128]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = Y11; # pin_io_B2_L32P2_GCLK29_Y11_J2_41 -> IO_FPGA_BANK2_IO0 NET "pin_gpio[129]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = AB11; # pin_io_B2_L32N2_GCLK28_AB11_J2_43 -> IO_FPGA_BANK2_IO1 # ############################################################################################################## # io bank 2 # valid IO pins for XC6SLX45, XC6SLX100, XC6SLX150 # ############################################################################################################## NET "pin_gpio[130]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U17; # pin_io_B2_L8P2_U17_J2_47 -> IO_FPGA_BANK2_OPT_IO0 NET "pin_gpio[131]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U16; # pin_io_B2_L8N2_U16_J2_45 -> IO_FPGA_BANK2_OPT_IO1 NET "pin_gpio[132]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V19; # pin_io_B2_L9P2_V19_J2_40 -> IO_FPGA_BANK2_OPT_IO2 NET "pin_gpio[133]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V18; # pin_io_B2_L9N2_V18_J2_38 -> IO_FPGA_BANK2_OPT_IO3 NET "pin_gpio[134]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R16; # pin_io_B2_L10P2_R16_J2_62 -> IO_FPGA_BANK2_OPT_IO4 NET "pin_gpio[135]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R15; # pin_io_B2_L10N2_R15_J2_64 -> IO_FPGA_BANK2_OPT_IO5 NET "pin_gpio[136]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U6; # pin_io_B2_L63P2_U6_J1_24 -> IO_FPGA_BANK2_OPT_IO6 NET "pin_gpio[137]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V5; # pin_io_B2_L63N2_V5_J1_22 -> IO_FPGA_BANK2_OPT_IO7 NET "pin_gpio[138]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V13; # pin_io_B2_L18P2_V13_J2_28 -> IO_FPGA_BANK2_OPT_IO8 NET "pin_gpio[139]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W13; # pin_io_B2_L18N2_W13_J2_26 -> IO_FPGA_BANK2_OPT_IO9 NET "pin_gpio[140]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W14; # pin_io_B2_L20P2_W14_J2_35 -> IO_FPGA_BANK2_OPT_IO10 NET "pin_gpio[141]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = Y14; # pin_io_B2_L20N2_Y14_J2_33 -> IO_FPGA_BANK2_OPT_IO11 NET "pin_gpio[142]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T14; # pin_io_B2_L23P2_T14_J2_34 -> IO_FPGA_BANK2_OPT_IO12 NET "pin_gpio[143]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R13; # pin_io_B2_L23N2_R13_J2_36 -> IO_FPGA_BANK2_OPT_IO13 NET "pin_gpio[144]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R11; # pin_io_B2_L40P2_R11_J1_68 -> IO_FPGA_BANK2_OPT_IO14 NET "pin_gpio[145]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T11; # pin_io_B2_L40N2_T11_J1_66 -> IO_FPGA_BANK2_OPT_IO15 NET "pin_gpio[146]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W10; # pin_io_B2_L44P2_W10_J2_39 -> IO_FPGA_BANK2_OPT_IO16 NET "pin_gpio[147]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = Y10; # pin_io_B2_L44N2_Y10_J2_37 -> IO_FPGA_BANK2_OPT_IO17 NET "pin_gpio[148]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W8; # pin_io_B2_L46P2_W8_J1_14 -> IO_FPGA_BANK2_OPT_IO18 NET "pin_gpio[149]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = V7; # pin_io_B2_L46N2_V7_J1_16 -> IO_FPGA_BANK2_OPT_IO19 NET "pin_gpio[150]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W9; # pin_io_B2_L47P2_W9_J1_9 -> IO_FPGA_BANK2_OPT_IO20 NET "pin_gpio[151]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = Y8; # pin_io_B2_L47N2_Y8_J1_11 -> IO_FPGA_BANK2_OPT_IO21 NET "pin_gpio[152]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R7; # pin_io_B2_L60N2_R7_J1_1 -> IO_FPGA_BANK2_OPT_IO22 NET "pin_gpio[153]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T7; # pin_io_B2_L60P2_T7_J1_3 -> IO_FPGA_BANK2_OPT_IO23 NET "pin_gpio[154]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R9; # pin_io_B2_L59P2_R9_J1_28 -> IO_FPGA_BANK2_OPT_IO24 NET "pin_gpio[155]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = R8; # pin_io_B2_L59N2_R8_J1_26 -> IO_FPGA_BANK2_OPT_IO25 NET "pin_gpio[156]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U9; # pin_io_B2_L50P2_U9_J1_12 -> IO_FPGA_BANK2_OPT_IO26 (single ended only) # ############################################################################################################## # io bank 2 # valid IO pins for XC6SLX45, XC6SLX150 # ############################################################################################################## NET "pin_gpio[157]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = Y16; # pin_io_B2_L17P2_Y16_J2_59 -> IO_FPGA_BANK2_OPT2_IO0 NET "pin_gpio[158]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W15; # pin_io_B2_L17N2_W15_J2_57 -> IO_FPGA_BANK2_OPT2_IO1 NET "pin_gpio[159]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T12; # pin_io_B2_L22P2_T12_J2_32 -> IO_FPGA_BANK2_OPT2_IO2 NET "pin_gpio[160]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U12; # pin_io_B2_L22N2_U12_J2_30 -> IO_FPGA_BANK2_OPT2_IO3 NET "pin_gpio[161]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T8; # pin_io_B2_L51P2_T8_J2_31 -> IO_FPGA_BANK2_OPT2_IO4 NET "pin_gpio[162]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U8; # pin_io_B2_L51N2_U8_J2_29 -> IO_FPGA_BANK2_OPT2_IO5 NET "pin_gpio[163]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = T10; # pin_io_B2_L52P2_T10_J2_25 -> IO_FPGA_BANK2_OPT2_IO6 NET "pin_gpio[164]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = U10; # pin_io_B2_L52N2_U10_J2_27 -> IO_FPGA_BANK2_OPT2_IO7 NET "pin_gpio[165]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = W6; # pin_io_B2_L53P2_W6_J1_7 -> IO_FPGA_BANK2_OPT2_IO8 NET "pin_gpio[166]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = Y6; # pin_io_B2_L53N2_Y6_J1_5 -> IO_FPGA_BANK2_OPT2_IO9 NET "pin_gpio[167]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = Y5; # pin_io_B2_L54P2_Y5_J1_20 -> IO_FPGA_BANK2_OPT2_IO10 NET "pin_gpio[168]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = AB5; # pin_io_B2_L54N2_AB5_J1_18 -> IO_FPGA_BANK2_OPT2_IO11 # ############################################################################################################## # io bank 0 # valid IO pins for XC6SLX100, XC6S150 # ############################################################################################################## #NET "pin_gpio[169]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = E8; # pin_io_B0_L14P0_E8_J1_54 -> IO_FPGA_BANK0_OPT_IO0 #NET "pin_gpio[170]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F8; # pin_io_B0_L14N0_F8_J1_56 -> IO_FPGA_BANK0_OPT_IO1 #NET "pin_gpio[171]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G8; # pin_io_B0_L15P0_G8_J1_70 -> IO_FPGA_BANK0_OPT_IO2 #NET "pin_gpio[172]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F9; # pin_io_B0_L15N0_F9_J1_72 -> IO_FPGA_BANK0_OPT_IO3 #NET "pin_gpio[173]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G9; # pin_io_B0_L16P0_G9_J1_64 -> IO_FPGA_BANK0_OPT_IO4 #NET "pin_gpio[174]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H10; # pin_io_B0_L16N0_H10_J1_62 -> IO_FPGA_BANK0_OPT_IO5 #NET "pin_gpio[175]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = E10; # pin_io_B0_L17P0_E10_J1_78 -> IO_FPGA_BANK0_OPT_IO6 #NET "pin_gpio[176]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F10; # pin_io_B0_L17N0_F10_J1_80 -> IO_FPGA_BANK0_OPT_IO7 #NET "pin_gpio[177]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G11; # pin_io_B0_L18P0_G11_J1_19 -> IO_FPGA_BANK0_OPT_IO8 #NET "pin_gpio[178]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H11; # pin_io_B0_L18N0_H11_J1_17 -> IO_FPGA_BANK0_OPT_IO9 #NET "pin_gpio[179]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = E12; # pin_io_B0_L43P0_E12_J1_53 -> IO_FPGA_BANK0_OPT_IO10 #NET "pin_gpio[180]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D12; # pin_io_B0_L43N0_D12_J1_55 -> IO_FPGA_BANK0_OPT_IO11 #NET "pin_gpio[181]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H12; # pin_io_B0_L44P0_H12_J1_38 -> IO_FPGA_BANK0_OPT_IO12 #NET "pin_gpio[182]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F12; # pin_io_B0_L44N0_F12_J1_40 -> IO_FPGA_BANK0_OPT_IO13 #NET "pin_gpio[183]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F13; # pin_io_B0_L45P0_F13_J1_33 -> IO_FPGA_BANK0_OPT_IO14 #NET "pin_gpio[184]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = D13; # pin_io_B0_L45N0_D13_J1_35 -> IO_FPGA_BANK0_OPT_IO15 #NET "pin_gpio[185]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H13; # pin_io_B0_L46P0_H13_J1_49 -> IO_FPGA_BANK0_OPT_IO16 #NET "pin_gpio[186]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = G13; # pin_io_B0_L46N0_G13_J1_51 -> IO_FPGA_BANK0_OPT_IO17 #NET "pin_gpio[187]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = E14; # pin_io_B0_L47P0_E14_J1_92 -> IO_FPGA_BANK0_OPT_IO18 #NET "pin_gpio[188]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F15; # pin_io_B0_L47N0_F15_J1_90 -> IO_FPGA_BANK0_OPT_IO19 #NET "pin_gpio[189]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = F14; # pin_io_B0_L48P0_F14_J1_69 -> IO_FPGA_BANK0_OPT_IO20 #NET "pin_gpio[190]" SLEW = SLOW | DRIVE = 4 | IOSTANDARD = LVCMOS33 | LOC = H14; # pin_io_B0_L48N0_H14_J1_71 -> IO_FPGA_BANK0_OPT_IO21 ############################################################################ ## ## Xilinx, Inc. 2006 www.xilinx.com ## Mi 14. Aug 11:05:23 2013 ## Generated by MIG Version 3.92 ## ############################################################################ ## File name : example_top.ucf ## ## Details : Constraints file ## FPGA family: spartan6 ## FPGA: xc6slx45-fgg484 ## Speedgrade: -3 ## Design Entry: VHDL ## Design: with Test bench ## DCM Used: Enable ## Compatible FPGA's: xc6slx25-fgg484,xc6slx75-fgg484,xc6slx100-fgg484,xc6slx150-fgg484 ## No.Of Memory Controllers: 1 ## ############################################################################ ############################################################################ # VCC AUX VOLTAGE ############################################################################ CONFIG VCCAUX = 2.5; # Valid values are 2.5 and 3.3 ############################################################################ # DDR2 requires the MCB to operate in Extended performance mode with higher Vccint # specification to achieve maximum frequency. Therefore, the following CONFIG constraint # follows the corresponding GUI option setting. However, DDR3 can operate at higher # frequencies with any Vcciint value by operating MCB in extended mode. Please do not # remove/edit the below constraint to avoid false errors. ############################################################################ CONFIG MCB_PERFORMANCE = STANDARD; ################################################################################## # Timing Ignore constraints for paths crossing the clock domain ################################################################################## NET "inst_mcb_ddr2/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG; NET "inst_mcb_ddr2/c?_pll_lock" TIG; INST "inst_mcb_ddr2/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG; #Please uncomment the below TIG if used in a design which enables self-refresh mode #NET "inst_mcb_ddr2/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG; NET "inst_mcb_ddr2/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only ############################################################################ ## Memory Controller 3 ## Memory Device: DDR2_SDRAM->MT47H128M16XX-25E ## Frequency: 333.333 MHz ## Time Period: 3000 ps ## Supported Part Numbers: MT47H128M16HG-25E;MT47H128M16RT-25E ############################################################################ ############################################################################ ## Clock constraints ############################################################################ #Will be automatically derived from 100 MHz clock driving the PLL #NET "inst_mcb_ddr2/memc3_infrastructure_inst/sys_clk" TNM_NET = "SYS_CLK3"; #TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3 ns HIGH 50 %; NET "pin_clk100_i" TNM_NET = "pin_clk100_i"; ############################################################################ ############################################################################ ## I/O TERMINATION ############################################################################ NET "mcb3_dram_dq[0]" IN_TERM = NONE; NET "mcb3_dram_dq[10]" IN_TERM = NONE; NET "mcb3_dram_dq[11]" IN_TERM = NONE; NET "mcb3_dram_dq[12]" IN_TERM = NONE; NET "mcb3_dram_dq[13]" IN_TERM = NONE; NET "mcb3_dram_dq[14]" IN_TERM = NONE; NET "mcb3_dram_dq[15]" IN_TERM = NONE; NET "mcb3_dram_dq[1]" IN_TERM = NONE; NET "mcb3_dram_dq[2]" IN_TERM = NONE; NET "mcb3_dram_dq[3]" IN_TERM = NONE; NET "mcb3_dram_dq[4]" IN_TERM = NONE; NET "mcb3_dram_dq[5]" IN_TERM = NONE; NET "mcb3_dram_dq[6]" IN_TERM = NONE; NET "mcb3_dram_dq[7]" IN_TERM = NONE; NET "mcb3_dram_dq[8]" IN_TERM = NONE; NET "mcb3_dram_dq[9]" IN_TERM = NONE; NET "mcb3_dram_dqs" IN_TERM = NONE; NET "mcb3_dram_dqs_n" IN_TERM = NONE; NET "mcb3_dram_udqs" IN_TERM = NONE; NET "mcb3_dram_udqs_n" IN_TERM = NONE; ############################################################################ # Status Signals ############################################################################ #MK NET "error" IOSTANDARD = LVCMOS18 ; #MK NET "calib_done" IOSTANDARD = LVCMOS18 ; #MK NET "calib_done" LOC = "C5" ; #MK NET "error" LOC = "A5" ; ############################################################################ # I/O STANDARDS ############################################################################ NET "mcb3_dram_dq[0]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[10]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[11]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[12]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[13]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[14]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[15]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[1]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[2]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[3]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[4]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[5]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[6]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[7]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[8]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dq[9]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[0]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[10]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[11]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[12]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[13]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[1]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[2]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[3]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[4]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[5]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[6]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[7]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[8]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[9]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_ba[0]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_ba[1]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_ba[2]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II; NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II; NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II; NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II; NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II; NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II; NET "mcb3_rzq" IOSTANDARD = SSTL18_II; NET "mcb3_zio" IOSTANDARD = SSTL18_II; #NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ; #NET "c3_sys_rst_i" IOSTANDARD = LVCMOS18 ; ############################################################################ # MCB 3 # Pin Location Constraints for Clock, Masks, Address, and Controls ############################################################################ NET "mcb3_dram_a[0]" LOC = H2; NET "mcb3_dram_a[10]" LOC = G4; NET "mcb3_dram_a[11]" LOC = C1; NET "mcb3_dram_a[12]" LOC = D1; NET "mcb3_dram_a[13]" LOC = G6; NET "mcb3_dram_a[1]" LOC = H1; NET "mcb3_dram_a[2]" LOC = H5; NET "mcb3_dram_a[3]" LOC = K6; NET "mcb3_dram_a[4]" LOC = F3; NET "mcb3_dram_a[5]" LOC = K3; NET "mcb3_dram_a[6]" LOC = J4; NET "mcb3_dram_a[7]" LOC = H6; NET "mcb3_dram_a[8]" LOC = E3; NET "mcb3_dram_a[9]" LOC = E1; NET "mcb3_dram_ba[0]" LOC = G3; NET "mcb3_dram_ba[1]" LOC = G1; NET "mcb3_dram_ba[2]" LOC = F1; NET "mcb3_dram_cas_n" LOC = K4; NET "mcb3_dram_ck" LOC = H4; NET "mcb3_dram_ck_n" LOC = H3; NET "mcb3_dram_cke" LOC = D2; NET "mcb3_dram_dm" LOC = L4; NET "mcb3_dram_dq[0]" LOC = N3; NET "mcb3_dram_dq[10]" LOC = R3; NET "mcb3_dram_dq[11]" LOC = R1; NET "mcb3_dram_dq[12]" LOC = U3; NET "mcb3_dram_dq[13]" LOC = U1; NET "mcb3_dram_dq[14]" LOC = V2; NET "mcb3_dram_dq[15]" LOC = V1; NET "mcb3_dram_dq[1]" LOC = N1; NET "mcb3_dram_dq[2]" LOC = M2; NET "mcb3_dram_dq[3]" LOC = M1; NET "mcb3_dram_dq[4]" LOC = J3; NET "mcb3_dram_dq[5]" LOC = J1; NET "mcb3_dram_dq[6]" LOC = K2; NET "mcb3_dram_dq[7]" LOC = K1; NET "mcb3_dram_dq[8]" LOC = P2; NET "mcb3_dram_dq[9]" LOC = P1; NET "mcb3_dram_dqs" LOC = L3; NET "mcb3_dram_dqs_n" LOC = L1; NET "mcb3_dram_odt" LOC = J6; NET "mcb3_dram_ras_n" LOC = K5; NET "mcb3_dram_udm" LOC = M3; NET "mcb3_dram_udqs" LOC = T2; NET "mcb3_dram_udqs_n" LOC = T1; NET "mcb3_dram_we_n" LOC = F2; ################################################################################## #RZQ is required for all MCB designs. Do not move the location # #of this pin for ES devices.For production devices, RZQ can be moved to any # #valid package pin within the MCB bank.For designs using Calibrated Input Termination, # #a 2R resistor should be connected between RZQand ground, where R is the desired# #input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.# ################################################################################## NET "mcb3_rzq" LOC = Y2; ################################################################################## #ZIO is only required for MCB designs using Calibrated Input Termination.# #ZIO can be moved to any valid package pin (i.e. bonded IO) within the# #MCB bank but must be left as a no-connect (NC) pin.# ################################################################################## NET "mcb3_zio" LOC = W3; #EOF