The UDK is a comprehensive concept to access FPGA boards with different host interfaces almost identically.
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On the host-side, there is a standardized API "CeUni.lib". On the FPGA-side a standardized 32-bit Wishbone-Bus interface is used. FPGA-designs and their associated PC-software run on all supported operating systems and all supported Cesys FPGA boards with no or minimal code changes. For customer specific develpments we also use the UDK. Code Example: |
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#include "usbuniapi.h" using namespace ceSystem; using namespace ceUSBUni; void DownloadDesign(ceDevice *pDev, const char *pszDesignName) { // load a FPGA design file ceFPGA FPGA; FPGA.LoadBin(pszDesignName); // download design and reset FPGA (internally called) pDev->ProgramFPGA(&FPGA); } void CheckWOProtocol(ceDevice *pDev) { // Program the FPGA DownloadDesign(pDev, "AnyUserDesign.bin"); uchar *pucBuffer = new uchar[256*1024]; // download 256k Data in FIFO mode uint uiRealTransfered = -1; pDev->WriteBulk(pucBuffer, 256*1024, uiRealTransfered); delete [] pucBuffer; } void CheckWProtocol(ceDevice *pDev) { // Program the FPGA DownloadDesign(pDev, "AnyUserDesignWithProtocol.bin"); uchar *pucBuffer = new uchar[256*1024]; // create protocol handler ceProtocol *pP = pDev->GetProtocol(); // download 256k Data in protocol mode (to address 0x20000000) pP->WriteBlock(0x20000000, pucBuffer, 256*1024); delete [] pucBuffer; } int main() { // begin of exception catch area try { // initialize API and search for USBV4F and EFM01 boards. ceUSBUniAPI::Init(ceDevice::ceDT_USBV4F); ceUSBUniAPI::Init(ceDevice::ceDT_EFM01); // check if any device is detected if(0!=ceDevice::GetDeviceCount()) { // access first device ceDevice *pDev = ceDevice::GetDevice(0); // open device for usage pDev->Open(); // Do something without protocol CheckWOProtocol(pDev); // Do some protocol transfer CheckWProtocol(pDev); // device not needed anymore, close it pDev->Close(); } else cout << "No device detected." << endl; } catch(ceException &e) { cout << e.What() << endl; } // deinitialize API ceUSBUniAPI::DeInit(); return 0; } For further information on Cesys FPGA boards or if you have questions, please visit our FPGA-Forum, send an E-Mail or call us: +49 9132 733 400. |