«The PCIeV4Base board is designed to meet today’s demands on development speed and flexibility. A powerful Virtex-4LX FPGA supplemented by a flexible PCI-Express controller enables developers to quickly complete their designs.»
The ExpressLane™ PEX 8311 1-lane PCI Express (PCIe) to 32-bit, 66MHz generic local bus bridge offers complete protocol translations between these two standards.
You can configure the FPGA using the Xilinx Platform Cable (JTAG), using your own UDK-based software, using the UDK3 board manager or from the on-board flash memory. All this options are always available - there is no need to choose with switches or jumpers.
The PCIVe4BASE FPGA board comes with the slot-board "PIB64IO" as default. It has 8 5-Volt tolerant buffers with 8 signals each. The buffer directions are switchable by FPGA io signals. For special requirements, you can develop your own custom PIB or ask to get an offer.
Included in the UDK, there are tools to perform FPGA configuration, send and receive data and control the reset-pin.
The Cesys UDK is an API for FPGA configuration and interfacing the FPGA to the software running on your PC. The UDK handles everything between a API call from your software and a Wishbone bus transaction inside the FPGA. Read and write calls are serialized through the PCIe interface, making the FPGA bus address space directly accessible by your software. Using the UDK results in an enormous saving in time and development resources. It is available at no additional cost when used with Cesys boards. To use it with 3rd party hardware, we offer a pay-once licensing model for the UDK source-code.
Use our extensively tested reference designs as a starting point for your projects. We use our own reference designs for many customer projects and can therefore offer you the very best support.
We have great interest in ensuring that your project is successful. That is why we will give great effort to assist you. We will answer questions that you ask in our support-forum as soon as possible because sometimes, it's the little things that stop you. In addition to our free forum-support, we offer fee-based support and development service customized to your needs.
The PCIeV4BASE was built for prototyping systems and integration into OEM devices.
|device||CLBs||equivalent logic cells||distributed RAM bits||block ram bits||XtremeDSP slices||dcms|
|XC4VLX25||96 x 26||24,192||168k||1,296k||481||8|
1 each XtremeDSP contains one 18x18 multiplier, an adder and an accumulator.
To develop your own FPGA solutions, Xilinx offers the ISE design suite. The XC4VLX Virtex-4® FPGA that is used on the PCIeV4BASE is supported by the free version, called WebPack Edition.
Get answers, download* drivers, tools and reference designs from the Cesys support forum.
* To enter the protected download area of the forum, you have to register in the forum and ask the forum admin to flag you as a customer.
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